1. Field of the Invention
The present invention relates to a carrier, and more particularly to a carrier capable of increasing a circuit layout space.
2. Description of Related Art
As shown in FIG. 1, a conventional chip package structure 100 having a cavity mainly includes a carrier 110, a first chip 120, a second chip 130 and an encapsulant 140. The carrier 110 is usually composed of a substrate 111 and a heat dissipating plate 112. The substrate 111 has an upper surface 113, a lower surface 114 and an opening 115. The heat dissipating plate 112 is adhered to the lower surface 114 of the substrate 111, such that the opening 115 of the substrate 111 may form the cell which is able to accommodate the chips. A plurality of first contacts 116, a plurality of second contacts 117 and a plurality of ball pads 118 are formed on the upper surface 113 of the substrate 111. A back surface 122 of the first chip 120 is adhered to a surface 119 of the heat dissipating plate 112. The second chip 130 is adhered to an active surface 121 of the first chip 120. A plurality of first bonding wires 150 is electrically connected to a plurality of first bonding pads 123 of the first chip 120 and the first contacts 116 of the substrate 111. A plurality of second bonding wires 160 is electrically connected to a plurality of second bonding pads 131 of the second chip 130 and the second contacts 117 of the substrate 111. The encapsulant 140 is formed on the upper surface 113 of the substrate 111, so as to encapsulate the first bonding wires 150 and the second bonding wires 160. A plurality of solder balls 170 is disposed on the ball pads 118, so as to externally connect a circuit board. In addition, the first contacts 116 and the second contacts 117 are formed on the same surface of the substrate 111. Hence, it is required to closely monitor the height of the first bonding wires 150 and that of the second bonding wires 160 for fear that a short circuit may occur due to a contact between the first bonding wires 150 and the second bonding wires 160. Based on the above, the encapsulant 140 may have a greater height, such that the chip package structure 100 has a comparatively significant thickness.